The Hailo Architecture


Rethinking Deep Learning Processing

Hailo’s revolutionary architecture is a clean-slate approach to the design of a specialized technology stack. It has created a domain-specific processor that vastly outperforms the Von Neumann architecture for deep learning tasks.

Hailo’s Structure-Defined Dataflow Architecture

Hailo delivers multiple innovations, addressing the fundamental properties of neural networks:

  • Innovative control scheme based on a combination of hardware and software reaches very low joules/operation with a high degree of flexibility
  • Distributed memory fabric with purpose-built pipeline elements that allows very low-power memory access in neural network processing
  • Extremely efficient computational elements that can be applied variably, as needed
  • Dataflow-oriented interconnect adapts to the structure of the neural network and allows high resource utilization
  • Hailo Dataflow Compiler – Full-stack software co-designed with the hardware architecture of the neural network processor enables efficient deployment of neural networks developed with seamless integration to existing frameworks

Neural Network Graph

Resource

processing

breakdown

Resource Graph

Physical

resource

mapping

Hailo-8 NN Core

Dynamic

configuration

and execution

Dataflow architecture using neural network processing

Hailo dataflow compiler is a flexible and adaptable tool that can handle diverse neural network models, regardless of complexity or layer count. It takes user models as an input, offers visual representations of network architecture, and does not affect the functionality of the toolchain

During the build flow, the Hailo dataflow compiler decomposes each network layer into the necessary computational elements. This process generates a resource graph that represents the target network.

The dataflow compiler maps the resource graph of the target network to the physical resources available on the Hailo device, creating a customized data pipeline for maximum performance and efficiency. This alignment allows the network to maximize the device capabilities, achieving optimal execution speed and resource utilization.

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