Hailo’s revolutionary architecture is a clean-slate approach to the design of a specialized technology stack. It has created a domain-specific processor that significantly outperforms the Von Neumann architecture for deep learning tasks.
Hailo delivers multiple innovations, addressing the fundamental properties of neural networks:
Innovative control scheme based on a combination of hardware and software reaching very low joules/operation with a high degree of flexibility
Innovative control scheme
Distributed memory fabric with purpose-built pipeline elements that allow very low-power memory access in neural network processing
Extremely efficient computational elements that can be applied variably, as needed
Dataflow-oriented interconnect adapts to the structure of the neural network and allows high resource utilization
Hailo Dataflow Compiler – full-stack software co-designed with the hardware architecture of the neural network processor, enabling efficient deployment of neural network models with seamless integration to existing frameworks
Resource processing breakdown
Hailo dataflow compiler is a flexible and adaptable tool that can handle diverse neural network models, regardless of complexity or layer count. It takes user models as an input, offers visual representations of network architecture, and does not affect the functionality of the toolchain
Physical resource mapping
During the build flow, the Hailo dataflow compiler decomposes each network layer into the necessary computational elements. This process generates a resource graph that represents the target network.
Dynamic configuration and execution
The dataflow compiler maps the resource graph of the target network to the physical resources available on the Hailo device, creating a customized data pipeline for maximum performance and efficiency. This alignment allows the network to maximize the device capabilities, achieving optimal execution speed and resource utilization.
