Rethinking Deep Learning Processing

Hailo’s revolutionary architecture is a clean-slate approach to the design of a specialized technology stack. It has created a domain-specific processor that vastly outperforms the Von Neumann architecture for deep learning tasks.

Hailo’s Structure-Defined Dataflow Architecture

Hailo delivers multiple innovations, addressing the fundamental properties of neural networks:

  • Innovative control scheme based on a combination of hardware and software reaches very low joules/operation with a high degree of flexibility
  • Distributed memory fabric with purpose-built pipeline elements that allows very low-power memory access in neural network processing
  • Extremely efficient computational elements that can be applied variably, as needed
  • Dataflow-oriented interconnect adapts to the structure of the neural network and allows high resource utilization
  • Hailo Dataflow Compiler – Full-stack software co-designed with the hardware architecture of the neural network processor enables efficient deployment of neural networks developed with seamless integration to existing frameworks
Neural Network Graph




Resource Graph




Hailo Processor
Architecture Drawing Static 2020-01

The Hailo Dataflow compiler receives the user model as an input. The image is merely an illustration, the toolchain is not bounded to specific network architecture or network depth.

As part of the build flow, the Hailo Dataflow compiler is breaking down each of the network layers to the required computational elements, generating a resource graph which is representing the target network.

The Hailo Dataflow compiler is matching the target network’s resource graph to the physical resources on the device, generating a customized data pipe for the target network.

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